14. Coprocessor 0
The TagHi and TagLo registers are 32-bit read/write registers used to hold the following:*1
- the primary cache tag and parity
- the secondary cache tag and ECC
- the data in primary or secondary caches for certain CacheOps
TagHi/Lo formats in the R10000 processor differ from those in the R4400 due to changes in CacheOps and cache architecture. R10000 formats depend on the type of CacheOp executed and the cache to which it is applied. The reserved fields are read as zeroes after executing an Index Load Tag or an Index Load Data CacheOp and ignored when executing an Index Store Tag or an Index Store Data CacheOp.
To ensure NT kernel compatibility, the TagLo register is implemented as a 32-bit read/write register. The value written by an MTC0 instruction can be retrieved by a MFC0 instruction, unless an intervening CACHE instruction has modified the content.
This section gives the TagLo and TagHi register formats for the following CacheOp and cache combinations:
- CacheOp is Index Load/Store Tag
- primary instruction cache operation
- primary data cache operation
- secondary cache operation
- CacheOp is Index Load/Store Data
- primary instruction cache operation
- primary data cache operation
- secondary cache operation
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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